1. Field of the Invention
The present invention relates to semiconductor devices for laminating multiple semiconductor chips in packages.
The present application claims priority on Japanese Patent Application No. 2007-313317, the content of which is incorporated herein by reference.
2. Description of Related Art
Due to recent progresses in high-speed processing, high-density structures, and highly-integrated constitutions, various types of packages of semiconductor devices (hereinafter referred to as laminated packages) have been developed to laminate multiple semiconductor chips therein.
Laminated packages are each designed such that multiple semiconductor chips are vertically laminated together while external input/output terminals thereof are aligned in a single direction, wherein semiconductor chips differ from each other in lengths of wiring with external input/output terminals. This causes differences of delay times applied to signals with respect to semiconductor chips. As signal processing of a semiconductor device speeds up, differences in delay times become apparent due to differences of wiring lengths; hence, it is difficult to speed up signal processing.
One example of the laminated package will be described in conjunction with FIGS. 5A and 5B, which show semiconductor devices 100 and 101 each encapsulated in a double density package (DDP). In each of the semiconductor devices 100 and 101, two semiconductor chips 103 and 104 are sequentially laminated on a single substrate 102 having a plurality of bumps 102a for inputting and outputting signals in connection with an external device (not shown), wherein they are connected to the substrate 102 via bonding wires 105 and 106.
In the semiconductor device 100 shown in FIG. 5A, the bonding wires 105 are wired through an opening 102b of the substrate 102 so as to connect the semiconductor chip 103 to the substrate 102. A resin 107b is formed to seal the substrate 102, the semiconductor chips 103 and 104, and the bonding wires 106 (for connecting the semiconductor chip 104 to the substrate 102). In addition, a resin 107a is formed to seal the opening 102b of the substrate 102 and the bonding wires 105. Both the resins 107a and 107b are composed of the same resin material. The bonding wires 106 are longer than the bonding wires 105.
In the semiconductor device 101 shown in FIG. 5B, both the bonding wires 105 and 106 are arranged above a surface 102c of the substrate 102.
Each of the semiconductor devices 100 and 101 is produced in such a way that the “first” semiconductor chip 103 is connected to the substrate 102 via the bonding wires 105; the “second” semiconductor chip 104 is laminated on the semiconductor chip 103; and then, the semiconductor chip 104 is connected to the substrate 102 via the bonding wires 106. Herein, the bonding wires 105 and 106 having different lengths are used to connect the semiconductor chips 103 and 104 to the substrate 102 in each of the semiconductor devices 100 and 101. This causes differences between delay times (applied to signals transmitted between the semiconductor chip 103 and the external input/output bumps 102a) and delay times (applied to signals transmitted between the semiconductor chip 104 and the external input/output bumps 102a).
The delay times depend upon capacitances and inductances of the bonding wires 105 and 106. Herein, capacitances depend upon dielectric constants of peripheral materials (including the resins 107a and 107b) and wiring areas of the bonding wires 105 and 106, while inductances depend upon the lengths of the bonding wires 105 and 106. It is possible to adjust the delay times occurring in the substrate 102 by changing the wiring lengths and the wiring areas.
In the DDP, however, it is necessary to adjust delay times caused by differences of lengths of the bonding wires 105 and 106 (which connect the semiconductor chips 103 and 104 to the substrate 102) in addition to the adjustment of delay times occurring in the substrate 102. This is because the ratio of the bonding wires 105 and 106 within the overall signal transmission path is relatively high in the DDP; hence, it is not possible to neglect delay times due to the bonding wires 105 and 106.
It is presumed that delay times due to the bonding wires 105 and 106 can be adjusted by changing the lengths and diameters of the bonding wires 105 and 106. However, it is difficult to change the lengths of the bonding wires 105 and 106. In addition, changing the diameters of the bonding wires 105 and 106 will likely cause negative influences to the reliability in connecting the semiconductor chips 103 and 104 to the substrate 102. Even when the lengths and diameters are changed, it is difficult to secure significant effects in adjusting delay times due to differences of lengths of the bonding wires 105 and 106.
To cope with the above drawback, various technologies have been developed and disclosed in various documents such as Patent Documents 1 to 3, which teach semiconductor devices capable of avoiding deterioration of signals by coating bonding wires with resins.                Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-259769        Patent Document 2: Japanese Unexamined Patent Application Publication No. S61-237455        Patent Document 3: Japanese Unexamined Patent Application Publication No. 2005-167160        
Patent Document 1 teaches a semiconductor device in which the surrounding area of the bonding wires for connecting wire conductors to semiconductor elements is coated with a resin whose dielectric constant is approximately identical to the dielectric constant of a substrate.
Patent Document 2 teaches a semiconductor device having a first resin layer for sealing a semiconductor chip and a second resin layer formed externally of the first resin layer, wherein the dielectric constant of the first resin layer is lower than the dielectric constant of the second resin layer.
Patent Document 3 teaches a semiconductor device having a multilayered wiring structure including insulating layers and wiring layers which are alternately laminated on a substrate. Herein, in the “vertically adjacent” wiring layers, the resistance of a higher layer is identical to or lower than the resistance of a lower layer, and the resistance of the uppermost layer is lower than the resistance of the lowermost layer. In the “vertically adjacent” insulating layers, the dielectric constant of a higher layer is identical to or higher than the dielectric constant of a lower layer, and the dielectric constant of the uppermost layer is higher than the dielectric constant of the lowermost layer.
The semiconductor devices disclosed in Patent Document 1 and Patent Document 2 are designed to improve transmission characteristics such as high frequency characteristics, while the semiconductor device disclosed in Patent Document 3 is designed to reduce delay times due to the small thicknesses in the wiring layers in the multilayered refining structure.
The present inventors have recognized that none of the foregoing semiconductor devices are incapable of significantly reducing delay times due to differences of lengths of bonding wires.